A High-Performance Bus Architecture for Strongly Coupled Interconnects

Michael N Skoufis1,  Kedar Karmarkaran1,  Themistoklis Haniotakis2,  Spyros Tragoudas1
1Southern Illinois University, 2University of Patras


Coupling and increasing wire resistance on interconnect fabrics undermine the speed of the transient electrical signals. A brute-force approach for a crosstalk-reduced design relies on increasing the distance of interconnects from each other and using additional repeated logic. A pipelined bus-architecture exploiting the existing electrical noise is proposed. Process variations are taken into consideration in the analysis. The proposed technique is validated for the 65nm and 90nm CMOS processes for interconnects of various lengths.