A Low-Power Double_Edge_Triggered Address Pointer Circuit for FIFO Memory Design

Saravanan Ramamoorthy1,  Haibo Wang1,  Sarma Vrudhula2
1Southern Illinois University, Carbondale, 2Arizona State University, Tempe


This paper presents a novel design of address pointer for FIFO (First-In-First-Out) memory circuits. Advantages of the proposed design include: reduced capacitive load on the pointer clock path, the use of a true singlephase clock, and double-edge-triggering clock scheme. The circuit has low power consumption, is immune to circuit racing conditions and suitable for high-speed operations. Techniques to implement clock gating in pointer circuit design for further reducing power consumption are also discussed. The proposed circuit is implemented with a 65nm CMOS technology and its performance is compared with previous pointer circuits.