With the advent of ultra deep-submicron (UDSM) regime of integrated circuits, the issues with circuit marginality related transient failures are on the rise. An example of such failures is the thermal hotspot-induced ones, which are common when a particular functional unit experiences high switching activity for a considerable duration. In this paper, we propose an on-line hotspot-induced transient failure testing scheme using the built-in self-test (BIST)-based approach which accurately distinguishes such a transient failure from a hard fail and greatly reduces the test cost by dissociating a tester from the test process. We apply the principle of Fmax testing based on frequency shmoo to obtain the maximum safe operating frequency for individual functional units in a chip. We also propose a DFT scheme to characterize the impact of a “hot” unit on its neighborhood and also the influence of a “hot” neighborhood on an otherwise “cold” unit in the reverse way. Thus the proposed architecture extends the capability of the conventional BIST to test a certain class of circuit marginality related transient failures with a very low hardware overhead.