A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design

Saurabh Sinha,  Asha Balijepalli,  Yu Cao
Arizona State University


A compact hand-calculation model for the Carbon nanotube transistor(CNFET) is presented. In this work, we develop the first hand calculation model to aid in first-order analysis of digital and analog applications. Based on the physical understanding of ballistic transport in carbon nanotube transistors and tunneling at the Schottky barrier contacts, we have a simple I-V expression that can predict the device behavior with varying process and bias conditions without any iterations. Using this model, we compare a CNFET with 22nm MOSFET in both digital and analog domains. We conclude that (1) a CNFET circuit can be more than 10X faster than 22nm CMOS; (2)there is 10X improvement in gm for comparable device dimensions and (3) 25-100X improvement in gDS for comparable saturation current. This simple, physics-based model is an efficient tool for analytical treatment of CNFET based circuits, revealing potential design opportunities in the analog domain.