Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation

Huifang Qin1,  Animesh Kumar1,  Kannan Ramchandran1,  Jan Rabaey1,  Prakash Ishwar2
1University of California, Berkeley, 2Boston University


In this paper we present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SRAM module is reduced from 550mV to 220mV. A novel error-tolerant architecture further reduces the minimum static-error-free VDD to 155mV. With a 100mV noise margin, a 255mV standby VDD effectively reduces the SRAM leakage power by 98% compared to the typical standby at 1V.