Practical Clock Tree Robustness Signoff Metrics

Anand Rajaram,  Raguram Damodaram,  Arjun Rajagopal
DDSP, Texas Instruments, Dallas


Clock tree synthesis is one of the most important and time consuming tasks in the design of high performance VLSI chips. An equally important and related task is that of clock tree analysis and signoff. Though simple and intutive metrics like skew and delays have been used to track clock tree quality, they are not sufficient for most practical purposes. For example, almost all the practical chip design involves timing closure at multiple corners. In such cases, tracking the quality of the clock tree at multiple corners becomes necessary. It may be argued that skew at these corners can be used as a signoff metric. However, corners are just a few points in the entire process space. As a result, good skews at a few corners does not necessarily mean that the clock tree quality is good at other process points. This is especially true for the sub 90nm techcnology nodes in use today. Ideally, skew distribution obtained using a full fledged SSTA on the clock trees can be used as a signoff metric. But in most practical cases, the distributions of process parameters etc. assumed by SSTA is either not valid or not available with accuracy at design time. Thus, there is a need to be able to assess the quality of the clock tree across the entire process space without having the complete information about all the process variations and process corners. In this work, we propose two metrics that can address the problem of clock robustness signoff. One of the two metrics is related to global variation effects and the other is related to local variation effects. These metrics can be used in three important ways. First, they can be used to determine during CTS whether the clock tree is good enough to go through rest of the backend flow or whether more tuning needs to be done to the clock tree. Second, they can be used to isolate any parts of the clock tree that behaves like a {\em hot spot} for clock skew across corners. Third, it can be used as a final signoff metric for clock tree to ensure that the tracking of the delays and skews can be expected to be good across all process points. We provide several experimental results from industry testcases demonstrating the utility of our metrics