University of North Texas

The gate leakage is a major source of power dissipation for nanoscale CMOS circuits. In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimization during architectural synthesis. The algorithm uses device-level gate leakage models for precharacterizing register-transfer level (RTL) datapath component library. The algorithm assumes the number and type of different functional units as resource constraints and minimizes the leakage delay product (LDP). The proposed algorithm is tested for different DKCMOS using several behavioral synthesis benchmarks for $45 nm$ technology node. The experiments show that average gate leakage reduction are $67.7\%$ and $80.8\%$ for SiO$_2$-SiON and SiO$_2$-Si$_3$N$_4$, respectively. Thus, DKCMOS technology is an attractive technique for gate leakage reduction while maintaining the circuit performance.