A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-$V_{DD}$ SoCs

Dhruva Ghai,  Saraju Mohanty,  Elias Kougianos
University of North Texas


Level converters are becoming overhead for the circuits they are being employed in. If their power consumption continues to grow, they will fail to serve the very purpose they were built for. In this paper we propose the application of a dual-$T_{ox}$ (DOXCMOS) technique for the power-delay optimization of a DC to DC voltage level converter under oxide thickness ($T_{ox}$) and transistor geometry constraints. The results show power savings of $83\%$ and delay improvement of $60\%$ over existing designs. The proposed level converter is capable of performing level-up/down conversion, and blocking of the input signal. The design is area optimal, with a minimum number of transistors. It is a robust design producing a stable output for voltages as low as $0.6V$ and loads varying from $10fF$ to $200fF$ for a $90nm$ technology. The average power dissipation of the converter with a $45fF$ capacitive load is $19.89 \mu W$. The entire design cycle has been carried out up to physical design, including parasitic re-simulation. The physical design is fault tolerant and cross-talk noise free, thus suitable for Design For Manufacturability (DFM). To the best of the authors' knowledge, this is the first universal level converter designed using a DOXCMOS technology for power-delay optimization.