Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations

Sherif Tawfik and Volkan Kursun
University of Wisconsin-Madison


Scaling of single-gate bulk MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the leakage power and enhanced device sensitivity to process variations. Double-gate MOSFET technologies mitigate these limitations by providing an excellent control over a thin silicon body with two electrically coupled gates. FinFET is the most attractive choice among the double-gate transistor architectures because of the self alignment of the two gates and the similarity of the fabrication steps to the existing standard CMOS technology. In this paper, new independent-gate-biased FinFET sequential circuits are evaluated for power consumption and speed characteristics at different process corners under parameter fluctuations in a 32nm FinFET technology. With the independent-gate FinFET latches and flip-flops, the total active mode power consumption, the clock power, the leakage power, and the circuit area are reduced by up to 47%, 32%, 37%, and 20%, respectively, while maintaining similar speed and data stability as compared to the circuits with tied-gate FinFETs across different process corners.