Recently current source models (CSMs) have become popular for use in standard cell characterization and static timing analysis. However, there has not been any detailed study of what aspects of the gate parasitics and DC current source behavior should be modeled for sufficient accuracy, and there have been no results reported incorporating a CSM with the above complexity into a timing analysis flow with reasonable runtime. This paper addresses these two limitations by investigating complexity/accuracy tradeoffs in CSMs. We then present a novel technique to perform fast, accurate waveform analysis using current source models. Timing analysis results on benchmark circuits show significantly reduced errors and error spreads compared to a traditional Thevenin-based flow. In terms of µ+sigma percentile, we gain by 20-150% in slew through this approach.