Error Protected Data Bus Inversion Using Standard DRAM Components

Maurizio Skerlj1 and Paolo Ienne2
1Qimonda AG, 2EPFL


Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialised memories or assume error free environments. This is either unrealistic or impractical in many industrial situations. In this paper, we propose an architecture which implements classic low power encoding but uses industry standard SDRAMs. Moreover, the low power encoding is combined with error-protection in order to extend the application to noisy channels or to the presence of soft and hard failures in the memory. Our experimental results, based on current consumption measurements of DDR2 DRAM components in mass production, show savings up to 31% on the I/O power and 6% of the total memory energy of a single channel memory system of 4GB at practically no cost.