Monday, March 17, 2007

9:00am 5:00pm


Rooms: Carmel/Monterey



Advanced Technology & Design Solutions in Design for Manufacturing Era


Chair & Moderator:

Rajiv Joshi, IBM T J Watson Research Center, NY




K. Maitra, AMD

Chris Kim, University of Minnesota

Robert Jones, Freescale

Subhasis Mitra, Stanford University

Hillary Hunter , IBM

Praveen Elakkumanan ,IBM



The promise of high-κ/metal gates From electronic transport phenomena to emerging device/circuit applications



Kingsuk Maitra, AMD


Recent advancements of gate stack engineering have enabled the introduction of high-k/metal gates into mainstream CMOS device applications for 45 nm and beyond technology space. In this talk, we take a critical look back into the key steps which made this possible with primary focus on transport phenomena in transistors in presence of high-k/metal gates. Against this backdrop, the interaction of high-k/metal gates with end of roadmap devices would be thoroughly explored. High-k/metal gates have interesting ramifications in the circuit space-from NBTI (negative bias temperature instability) to high-field mobility, the high-k gate induced physical phenomena and their impact on device and circuit performance and reliability would be discussed. To conclude, this talk would also conjecture on the continued scalability of high-k gate stacks for futuristic CMOS device architectures.  



Low Voltage Circuit Design Techniques for Sub-32nm Technologies



Chris Kim

University of Minnesota


In order to continue CMOS scaling towards the physical limit, care must be  taken to account for each obstacle that is currently impeding our progress.  Increased power consumption and faster current transients have deteriorated on-chip power supply integrity.  Long term reliability issues such as  Negative Bias Temperature Instability (NBTI) have become serious problems degrading the performance and yield of high performance systems. This talk  will focus on circuit design techniques to deal with power supply noise and  aging issues in sub-32nm technologies.  First, I will present modeling and design techniques for reliable on-chip power supply delivery.  Next, an overview of several reliability mechanisms will be given followed by some recent developments on monitoring techniques to accurately measure and model the circuit aging impact.




Process Technology Development and New Design Opportunities

in 3D Integration Technology



Robert E. Jones



 3D integration offers inter-strata interconnect with high connectivity density, low parasitics, and shorter lengths.  This bring advantages in increased interconnect bandwidth, reduced interconnect latency and reduced power consumption in comparison with individual packaged chips on a board or packages with wire bonded stacked die.  3D integration can compete with, or even surpass, SoC (system on a chip) integration in terms of interconnect performance while allowing for differentiated process technologies for the various strata.

The key process technologies for 3D integration are (1) bonding of strata, (2) inter-strata electrical connections, (3) through strata vias (TSVs), and (4) strata thinning and thin strata handling.  A number of techniques had been explored for each of these key processes, and there various schemes for their order of integration.  The major options for integration architecture are wafer-to-wafer, die-to-wafer, and die-to-die.  The choice of architecture interacts with device application needs and device costs as well as the required process technologies.  Wafer-to-wafer has the advantage of bonding a large number of die in parallel and in providing a planar surface for subsequent processing.  Die-to-wafer (or die-to-die) has advantages in offering the ability to combine die of different areas and to integrate known good die while having the disadvantage of being a serial process

A number of design issues and opportunities arise for 3D integration.  A primary design architecture decision is how to partition the overall system between strata.  A simple partitioning strategy is to have a different circuit on each stratum (e.g. memory on logic).  Finer partitioning is required at the IP block level which generally are connected by global interconnect.  More complex partitioning could be within an IP block or even within the logic, memory or imager cell level.  In addition to requiring higher TSVs and inter-strata connections, a finer partitioning will usually require more advanced 3D design tools including routing, layout, and verification.  Additionally, it will also tend to make testing of individual die more difficult. By its nature 3D integration reduces the overall surface area/circuit area, and thus can further constrain thermal and electrical connectivity to the package.   Thermal aware design tools may be needed to minimize stacking of hot spots on top of each other.  3D integration can reduce overall power requirements by reducing interconnect lengths and parasitics.  In comparison with SiP integration, 3D can utilize lower voltages for circuit-to-circuit signals to further reduce power and latency.  Adding the third dimension to layout opens up new opportunities for the design to reduce critical signal path lengths.  When 3D integration is used to fabricate complex systems there will be an additional emphasis on improving built-in self-test and repair. 

3D integration is expected to move to volume production in the near future for imagers and stacked memories and later to memory on logic applications.  While some applications may select 3D for performance advantages or for reduced form factor, most product applications will be interested in 3D integration which is cost effective.  3D integration by its nature involves additional process costs for the 3D specific features and bonding.  However, 3D offers potential savings over SoC integration through (1) process differentiation, and (2) ability to assemble known good die.  The most advantageous systems for 3D integration will be those for which these savings outweigh the added process costs.



Robust System Design in Scaled CMOS 



Subhasis Mitra, Stanford University


Our central vision is: Develop enabling technologies and tools spanning multiple abstraction levels to design globally optimized robust systems without incurring the high cost of traditional redundancy. Specific ideas that will be discussed include:


  1. Built-In-Soft-Error Resilience: An architecture-aware circuit design technique corrects radiation-induced soft errors in latches, flip-flops, and combinational logic at  extremely low-cost compared to redundancy techniques;

  2. Circuit failure prediction and self-correction: A new design technique, distinct from error detection, predicts failures before they actually create errors in system data  and states. Circuit failure prediction is ideal for reliability mechanisms such as transistor aging and early-life failures, and can enable close to best-case design by minimizing traditional worst-case speed guardbands.


Caches in the Many-Core Era:  What Purpose Might eDRAM Serve?



Hillary Hunter , IBM


 Choosing data storage arrays for a microprocessor design is driven by a delicate balance of technology readiness, circuit-level design factors, and system-level performance, power, and scaling implications.  Recently, CMOS technologists have warned of the "end of scaling," and cite particular concern for six-transistor SRAM.  This is a startling forecast, since easily 50% of microprocessor silicon area is commonly occupied by SRAM caches.  A particularly long-standing debate has surrounded one dense, resilient, on-chip storage alternative: embedded DRAM. This tutorial will provide background on eDRAM, and show how its circuit and technology properties translate to metrics used to make decisions at the chip and architecture levels: cache capacity, cache access latency, and cache distance from the CPU. 




Enhancing Yield through Design for Manufacturability (DFM)



Praveen Elakkumanan, and Rajiv Joshi IBM


 This part of the tutorial will discuss in detail the manufacturing challenges in nanoscale VLSI and consequent Design for Manufacturability (DFM) approaches by taking a holistic approach in analyzing and addressing different process variability effects. We review the dominant process variations in semiconductor manufacturing process that affect the design yield, show their impact on layout quality, and present currently practiced DFM techniques to mitigate the effect of these variations. We also discuss various manufacturing-aware physical and circuit design methodologies and techniques for parametric yield improvement. This includes correct-by-construction methodologies such as Restricted Design Rules (RDRs) as well as manufacturing aware design approaches. In addition, we will briefly mention some of the many accepted and possible mitigation techniques in design post processing (after tape-out) and will introduce the concept of Manufacturing for Design (MFD) through design-intent processing.


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