Plenary Session 1P
Tuesday March 17
Dr. Chi-Foon Chan
President& COO, Synopsys
Plenary Speech 1P.1
Tuesday, March 17
Beyond CMOS: The Age of Partnerships
In less than 10 years our industry has matured considerably. We no longer chase performance through scaling but design sophisticated multi-disciplined systems. Design challenges such as power and signal integrity that were only secondary concerns are now primary. Critical dimensions are measured in multiples of atoms, and the design process is costly and resource hungry across all stages. Today we are pushing the limits of physics at 22nm and below.
Beyond CMOS we see increasingly complex designs that are merging analog with digital and wireless, including MEMS and other organic-based materials encapsulated in SIPs. How will we accomplish this level of design complexity while maintaining high quality, reliability and low cost development in ever-narrowing market windows? The designs of tomorrow require broad-based partnerships and alliances that surpass today’s practices and incorporate all players working closely from product inception to completion.
About Chi-Foon Chan
Dr. Chi-Foon Chan is the president and chief operating officer of Synopsys. In this role he shares responsibility for running the company with Synopsys chairman and CEO Dr. Aart de Geus. Dr. Chan is focused on driving the company's internal operations and worldwide field organization. He joined Synopsys in 1990 as vice president of Applications and Services. Previously at NEC Corporation, Dr. Chan was general manager of the microprocessor group, responsible for marketing all NEC chip devices in North America. Prior to NEC, Dr. Chan was an engineering manager at Intel Corporation. He holds an M.S. and a Ph.D. in Computer Engineering from Case Western Reserve University.
Plenary Speech 1P.2
Tuesday, March 17
Predictability Is Key to Quality Design
Chairman and CEO
Magma Design Automation
In semiconductor design, predictability provides the ultimate metric of the design process. The highest quality can never be achieved without a truly predictable design flow. What does such a flow require? Various approaches, ranging from wireload models to topological analysis, have been used to try to estimate during logic synthesis what will happen during physical design - but have always come up short. Systems on Chip (SoCs) always contain large macros, which make estimates based on wireload models or topological analysis useless. A truly predictable flow should be able to take clock and power into account throughout placement, optimization and routing. Finally, when assembling the SoC, the flow needs to be able to handle mixed-signal blocks in a predictable fashion. Engineering is an exact science. Estimates are for statisticians, yet, that's all that today's "state-of-art" flows deliver. While heuristics are useful, a solution built using only heuristics will not deliver high quality IC design. The Electronic Design Automation industry should develop exact methods and algorithms that enable predictable flows. This is especially important in turbulent economic times where time, money and manpower are in extremely short supply.
About Rajeev Madhavan
Rajeev Madhavan has served as Magma's Chief Executive Officer and Chairman of the Board of Directors since he co-founded the company in 1997, and also served as president until 2001. Madhavan presently serves on the board of directors for the Electronic Design Automation Consortium. Prior to founding Magma, he co-founded and served as President and CEO of Ambit Design Systems, Inc. and co-founded and served as Director of Engineering of LogicVision, Inc. Madhavan received a bachelor's degree in electronics and communication from KREC, Surathkal, India, and a master's degree in electrical engineering from Queen's University, Ontario, Canada.
Plenary Speech 1P.3
Tuesday, March 17
The P*3 of ESL: Productivity, Performance, Power
Vice president and General Manager of the Design and Synthesis Division
Mentor Graphics Corporation
ESL is steadily making inroads into production design flows to meet the surging challenges of SOC design. Overall, designer productivity is threatened by ever increasing challenges in design and verification due to the demands of deep submicron design. At the same time, the transition of more functionality to software and multi-core processors is threatening IC performance, while architectural decisions regarding power are being made too late in the design process. In all these areas, ESL can and is making a major impact. In this keynote, Simon Bloch will address the new and maturing ESL tools and methodologies, combined with the emerging TLM standards, that are providing a powerful approach for improving design quality, providing faster verification and design times, validating hardware dependent software and optimizing for low power. In other words, ESL offers a powerful and tangible ROI where IC designers need it the most: in productivity, performance and achieving lower power goals.
About Simon Bloch
Simon Bloch has served as general manager of the Design and Synthesis Division at Mentor Graphics since 2002. He is responsible for design and synthesis products for HDL and ESL. Prior to Mentor he held senior management positions at Aristo Technology, Compass Design, VLSI Technology and Daisy Systems working on IC design technologies in the front end and physical flows. Prior to EDA he designed ASICs and systems in telecommunication applications. Bloch has a BSEE from Tel Aviv University majoring in microelectronics, computers, and medical engineering.