Plenary Session 2P
Wednesday March 18
Dr. Chi-Foon Chan
President& COO, Synopsys
Plenary Speech 2P.1
Wednesday, March 18
High Performance Graphics in a Consumer SoC:
How to fit it into your system without squeezing everything else out
US Director of Business Development
Imagination Technologies, Inc.
High performance graphics has gone mainstream in a range of embedded devices. Driven in large part by the fact that for a consumer, the user interface is the device and the primary user interface is visual, in less than a year the discussion has moved on from whether to include hardware acceleration to how much acceleration is needed to compete; whereas the level of graphics was previously defined by the limitations of the system, now the system is being redefined by the need to provide compelling graphical interfaces. Having been given the task of coming up with a graphics enabled device, the first problem the architect must confront is simply fitting the technology into the system: the driving forces in embedded design are still cost, power efficiency and simplicity, so how can a technology which has developed in an environment largely insulated from these forces be modified to meet these unchanging criteria? This talk will take a look at some of the ways in which performance-efficient techniques can also deliver power and bandwidth-efficiencies sufficient to minimize some of those problems. We will take a look at what sort of power efficiency improvements can be delivered by hardware and what can be expected in terms of bus and memory interface loadings from some typical graphical operations. Next, we will turn to the effect on firmware of adding a new accelerator into the system. With a simple CPU driven interface, the software task is manageable without the need for an extensive infrastructure but with the user expectation of fancy animated graphics which mixes in video and other multimedia, the need for a uniform framework of interoperable firmware becomes critical. The second theme of the talk will be to survey the standard APIs which make this possible, focusing on the open standard APIs managed and promoted by Khronos. Last but equally important, is the ecosystem of tools and applications available to OEMs which will allow them to differentiate and add value to the graphical platform you have given them. This, for the consumer, is where the rubber hits the road and the extra cost of graphics is repaid by the improved useability and functionality of the end device. We will take a look at the kind of tools you should expect from a graphics vendor, and we will survey content creation and management applications out there which will help to deliver that extra value.
About Peter McGuinness
Peter McGuinness is US Director of Business Development at Imagination Technologies, Inc. a London Based company specialising in the development and licensing of hardware and software intellectual property for the mobile and consumer electronics markets. Since 1984 he has been involved in the design of graphics and video chips with Inmos, STMicroelectronics and Nvidia and has been well placed to observe the evolution of graphics adapters from standalone systems, able to call on dedicated resources and unlimited power budgets, to tightly integrated subsystems which are required to 'play nice' in resource constrained real-time multimedia SoCs.
Plenary Speech 2P.2
Wednesday, March 18
45nm and Beyond: Why the Process Technology Drove the Paradigm Shift in Design
Senior Vice President
The semiconductor industry has been cost-driven from the start, as evidenced by the adherence to Moore’s Law for the past 40 years. Three waves of effort, with some overlap, have bought us to logic and memory production at sub-50nm feature sizes. The first wave was scaling, enabled by the continual availability of better and better process equipment at slowly escalating costs. Especially in lithography, new exposure tools with higher resolution, and new etch tools (remember the “writing in stone” part?) with better selectivity and uniformity enabled the relentless reduction in feature sizes by over 100x. The second wave was materials, which permitted electrical performance to keep pace with scaling. Lower resistivity conductors such as copper and various silicides, and lower permittivity dielectrics such as CDO and air, have allowed device interconnects to scale. Higher permittivity dielectrics are getting MOS transistor scaling back on track. But now we are seeing the third wave. This is the paradigm shift in design caused by process technology reaching economic and physical limits. Deep subwavelength optical lithography won’t be economically replaced by EUV, in spite of 15 years of forecasts to the contrary. On-wafer structures are less and less like what is drawn in a CAD tool, making predictive simulation less accurate. Devices dimensions are reaching atomic limits, and new device models are needed to reflect the reality of variations like random dopant fluctuation. IC design has been successful in part because different levels of abstraction could be isolated and dealt with individually, with only minimal interactions with factors more that one level away. Without this kind of isolation, we will end up with system design engineers worrying about the numerical aperture of scanner lenses. In order to archive yieldable designs based on the structure of the abstraction of complex system level design, new components need to be created at multiple levels. This presentation will highlight some of the process technologies that are being implemented at 45nm and beyond. This will include the why and what of device, cell, macro, and routing architecture changes and their impact on the design methodologies in use today to create and validate a design.
About Mike Smayling
Dr. Smayling is an industry veteran with over 30 years of experience. He received a BS degree from the University of Minnesota, and MS and PhD degrees from Rice University, all in electrical engineering. He is currently a senior vice president at Tela Innovations responsible for technology development and integration. Prior to joining Tela, he was the CTO of the Maydan Technology Center at Applied Materials where he developed advanced processes for sub-45nm technology nodes. Before moving to Silicon Valley with Applied, he was a TI Fellow at Texas Instruments responsible for DRAM, Flash, and mixed-signal technology development and productization. He holds over 90 U.S. patents, and has >50 publications/presentations covering DFM, MOS devices, processes, Flash memory, LDMOS transistors, photolithography, and lasers. He was a lecturer at Rice University for over 10 years while at TI. He is a Senior Member of IEEE, and represented TI and Applied at SRC.
Plenary Speech 2P.3
Wednesday, March 18
Weathering the Storm: Fortifying Memory Storage through the Global Recession
Vice President of Memory Marketing
Given challenging market conditions, Samsung is looking at 2009 as a pivotal year in which to promote memory storage growth sectors that are less prone to market volatility. This keynote by Samsung Semiconductor Vice President Jim Elliott will highlight what is working for memory storage providers today and the opportunities that are beyond the horizon. Mr. Elliott will examine up-and-coming memory storage solutions including the rapidly expanding solid state drive (SSD) market and the increasing use of embedded NAND flash chips. In particular, his presentation will highlight how market conditions, higher densities and improved performance are pushing SSDs to the forefront of new storage solutions. The presentation will also discuss why the market is ripe for consolidation, and underscore the increased importance of vertical integration and strategic alliances.
About Jim Elliott
Jim Elliott, as Vice President of Memory Marketing at Samsung Semiconductor, Inc., oversees all marketing activities for Samsung’s memory organization in the Americas. Elliott has more than 12 years of experience in the semiconductor industry, during which he focused on product sales and marketing at major multinational companies. He started his semiconductor career in 1996 at Hitachi in SRAM Marketing. In late 1997, he transitioned into the volatile world of DRAM when he joined Fujitsu Microelectronics. Elliott has been at Samsung for the past six years, where he has held leadership positions in DRAM and Flash Marketing, as well as Global Accounts Sales. Elliott earned a Bachelor of Arts degree from the University of California at Davis and later received a Master’s degree in Business Administration from California Polytechnic University in San Luis Obispo. He has been a featured guest speaker at a number of industry-wide events, including the Intel Developer Forum, MemCon, StorageVisions and the Flash Memory Summit.