New Subthreshold Design Concepts in 65nm CMOS Technology

Farshad Moradi1,  Dag Wisland1,  Hamid Mahmoodi2,  Ali Peiravi3
1University of Oslo, 2San Francisco State University, 3Ferdowsi University of Mashhad


In this paper challenges observed in 65nm technology for circuits utilizing subthreshold region operation are presented. Different circuits are analyzed and simulated for ultra low supply voltages to find the best topology for subthreshold operation. To prove the simulation results some topologies are simulated based on the results. Various aspects of flip-flop circuits are described in detail to study which topology would be most suitable for Ultra low supply voltage and power applications. Simulation results show that the power consumption decreases by at least 23% compared with other flip-flops. Also, the setup time and the hold time are improved.