Statistical static timing analysis (SSTA) is indispensable for nanometer manufacturing under process variability. The process variations cause significant uncertainty in VLSI circuit timing and this makes yield control and timing verification a very difficult challenge. SSTA is suitable for timing estimation and design for manufacturability under process variation. However, most of the existing SSTA techniques have difficulty in keeping closed-form expressions after max operations and sum operations on variation sources. For computing a converged statistical form after max operations and sum operations, we propose an analytical approach which innovates the concept given by first-order canonical form and skew-normal distribution to solve this problem. These derived results are in closed-form and precise when timing sources have the skew-normal distribution or normal distribution. Experimental results show that, compared to the Monte-Carlo simulation, our approach estimates the timing constraint and predicts the yield within 1.5% and 0.2% error, respectively.