An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process

Karthik Rajagopal,  Aatmesh Aatmesh,  Vinod Menezes
Texas Instruments


The aggressive scaling of CMOS process is central to the continued performance enhancement of microprocessors. While the process scales every generation the I/O interface standards do not change at the same rate. This introduces a host of reliability issues. One not only needs to design for performance, but should also meet the reliability goals in the scaled technology for these standards. This paper presents a 3.3V I/O buffer designed using 1.8V transistors in a 65nm bulk CMOS process. Proposed I/O uses a novel differential amplifier based pre-driver topology, which has excellent gate-oxide reliability, runs at 200MHz and has comparative area and static power of an equivalent I/O in 65nm 3.3V CMOS process.