A Case Study on Logic Diagnosis for System-on-Chip

Youssef Benabboud1,  Alberto Bosio1,  Patrick Girard1,  Serge Pravossoudovitch1,  Arnaud Virazel1,  Laroussi Bouzaida2,  Isabelle Izaute2


This paper presents an industrial case study on logic diagnosis targeting System-on-Chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on the Effect-Cause paradigm. This approach consists of two phases: (i) a fault localization phase resorting to the critical path tracing to determine a set of suspects, (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. To deal with SoC we define a new algebra for the critical path tracing process during fault localization. Experimental results show the diagnosis accuracy, in terms of absolute number of suspects, of the proposed approach. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.