A Unified Gate Sizing Formulation for Optimizing Soft Error Rate, Cross-talk Noise and Power under Process Variations

Koustav Bhattacharya and Nagarajan Ranganathan
Dept. of CSE, USF


The trends in technology scaling have made nanometer designs highly susceptible to reliability threats like soft errors and crosstalk noise while uncertainty in process parameters have made the physical realization of devices and interconnects unpredictable. The limitations in manufacturing processes and the impact of environmental noise poses a major threat to the signal quality, and hence the realization of reliable, low-power, high performance designs with acceptable parametric yields is a challenging problem. Most noise analysis and prevention techniques reported in the literature target single noise sources. However, reliability issues like crosstalk noise and radiation induced soft errors are deeply inter-related. Further, manufacturing variations have decreased the efficacy of online detection and correction schemes used for traditional noise optimization. In this work, we have proposed a methodology for simultaneous optimization of soft error rate(SER), crosstalk noise and power of circuits with delay constraints under process variations. Soft errors are modeled using a novel first order analysis model while crosstalk noise is modeled at the logic level using clustering based on Rent's exponent. The proposed multi-metric gate sizing methodology have been formulated into a mathematical program and has been efficiently solved. Experimental results on ISCAS'85 benchmark circuits indicate significant improvements in SER, crosstalk noise and timing yield compared to the corresponding constrained optimization problems.