A Software Pipelining Algorithm in High-Level Synthesis for FPGA Architectures

Lei Gao1,  David Zaretsky2,  Gaurav Mittal2,  Dan Schonfeld1,  Prith Banerjee3
1University of Illinois at Chicago, 2BINACHIP Inc., 3HP Company


In this paper, we present a variation of the Modulo Scheduling algorithm to exploit software pipelining in the high-level synthesis for FPGA architectures. We demonstrate the difficulties of implementing software pipelining for FPGA architectures, and propose a modified version of Modulo Scheduling that addresses memory resource conflicts and the circular dependencies. The experimental results demonstrate significant speedups as compared to the non-pipelined high-level synthesis results and the software-pipelined results using traditional Modulo Scheduling algorithm.