Power Consumption in VLSI circuits is currently a major issue in the semiconductor industry. Power is a first order design constraint in many applications. However, a growing class of applications need extreme low power but do not need high speed. Sub-threshold circuit design can be used for these applications. Unfortunately, sub-threshold circuits exhibit an exponential sensitivity to process, voltage and temperature (PVT) variations. In this paper we implement and test a robust sub-threshold design flow which uses circuit level PVT compensation to stabilize circuit performance. We design and fabricate a sub-threshold BFSK transmitter chip. The transmitter is specified to transmit baseband signals up to a data rate of 32kbps. Experiments using the fabricated die, verify the functionality of the design show that the sub-threshold circuit consumes 19.4X lower power than the traditional standard cell based implementation on the same die.