An Abstraction Mechanism to maximize stimulus portability across RTL, FPGA, Software models and Silicon of SoCs

Mrinal Bose,  Prashant Naphade,  Jayanta Bhadra,  Hillel Miller


SoC verification efforts involve multiple models of the design RTL, FPGA, silicon and software models. With increasing design complexity, re-use of tests between models is a must. In this paper, we introduce a stimulus abstraction mechanism which greatly increases the re-usability of tests across models. We then demonstrate an implementation of the abstraction mechanism on two models of a PCI-Express based design. Identical tests are used to drive an RTL model via a BFM and a software model via stream sockets to achieve the same result.