Control of Design Specific Variation in Etch-Assisted Via Pattern Transfer by Means of Full-Chip Simulation

Valeriy Sukharev1,  Armen Kteyan1,  Ara Markosian1,  Jun-Ho Choy1,  Nikolay Khachatryan1,  Henrik Hovsepyan1,  Hasmik Lazaryan1,  Seiji Onoue2,  Takuo Kikuchi2,  Tetsuya Kamigaki2
1Mentor Graphics Corporation, 2Toshiba Corporation


A novel model-based algorithm provides a capability to control full-chip design specific variation in pattern transfer caused by via/contact etch processes. This physics based algorithm is capable to detect and report etch hotspots based on the fab defined thresholds of acceptable variations in critical dimension (CD) of etched shapes for a prospective dry etch process step. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel via-contact etch (VCE) EDA tool for the design aware process optimization in addition to the “standard” process aware design optimization.