We explore two schemes using transmission-line (T-line) to achieve high-performance global interconnects on VLSI chips. For both schemes, we devise wire dimension to expose T-line effect and employ the inverter chain as the driver and receiver. In order to achieve high throughput and alleviate the Inter-Symbol Interference (ISI), the termination resistance is added on the second scheme. For the two schemes, firstly we discuss how to choose the wire dimension and effects of driver impedance and termination resistance on the wire bandwidth. Secondly, the design methodologies are proposed to determine the optimal design variables under three objectives. We adopt the methodology to design two schemes and compare the performance metrics with repeated RC wires. Simulation results show that, the proposed T-line schemes reduce the delay, power consumption and improve the throughput as much as 82%, 21% and 45%, under min-ddp (delay^2-power product) objective.