Robust Differential Asynchronous Nanoelectronic Circuits

Bao Liu


Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and significant parametric variations. Asynchronous circuits have the great potential to achieve delay insensitive, high performance and low power nanoelectronic design, while the existing asynchronous circuits do no achieve reliability in the presence of glitches. In this paper, I propose robust asynchronous circuit design, which combines asynchronous design for delay insensitiveness, differential logic for redundancy, and error correction coding for resilience. Theoretical analysis and SPICE simulation with 22nm CMOS Predictive Technology Models show that the proposed robust differential asynchronous circuit design achieves (1) logic correctness at the event of a single bit soft error or a common multiple bit soft error by differential logic and error correction coding, and (2) timing correctness for any delay variation given physical proximity of the components in the circuit.