A Study on Impact of Loading Effect on Capacitive Crosstalk Noise

Alodeep Sanyal,  Abhisek Pan,  Sandip Kundu
ECE Department, University of Massachusetts at Amherst


Decreasing process geometries and increasing operating frequencies have made VLSI circuits more susceptible to signal integrity related failures. Capacitive crosstalk is one of the major causes for such kind of failures. Typically, crosstalk faults result from switching of neighboring lines that are capacitively coupled. As we move deep into nanometer regime, transistor gate leakage introduces considerable voltage noise in internal circuit nodes. This phenomenon is known as loading effect. The objective of this paper is to study the impact of this voltage noise on capacitive cross-talk related signal integrity problems. A simplified cross-talk analysis system assumes that all aggressors of a net can switch at the same time. This leads to excessive pessimism that can be reduced by considering the timing window of aggressor switching as well as their Boolean relationships. In order to evaluate the impact of loading effect on cross-talk noise, we devised a dynamic simulator that performs dynamic timing simulation. By performing simulations on ISCAS-85 benchmark circuits we established that loading effect is a significant aggravator of cross-talk noise that leads to increased number of failures. The main contributions of this paper are (i) showing that loading effect worsens cross-talk related signal integrity problems and (ii) an efficient dynamic timing simulator for simulating crosstalk effects that provide a quantities measure.