A General Piece-wise Nonlinear Library Modeling Format and Size Reduction Technique for Gate-level Timing, SI, Power, and Variation Analysis

Xin Wang,  Alireza Kasnavi,  Harold Levy
Synopsys Inc


Standard cell libraries are used extensively in CMOS digital circuit designs. In the past ten years, standard cell library size has increased by more than 10X. It is becoming a must to reduce the library size. In this paper, we present an efficient piece-wise nonlinear library modeling format and library size reduction technique. Instead of using tables and vectors, this format uses base templates (curve or surface templates) to model the shape of curve or surfaces. It works very well for standard Cells that exhibit similar behaviors. It is also efficient because the shape can be modeled by a single id. This technique can be applied to timing, SI, power, and variation modeling. It can be directly applied to the traditional Nonlinear Delay Model and the recently developed Current Source Models. This paper also presents a fast method for efficiently selecting the optimal template and detecting bad library data. Several examples are provided in this paper to show this technique is generic, robust, and efficient. Results show .lib library size can be reduced by 5~10X. Experiments using an industry-leading STA tool show the impact on accuracy is ignorable. This technique also help reduces STA tool memory usage and improves runtime.