A New Approach to Detect Logic Soft Errors in Digital Circuits

Hai YU,  Michael Nicolaidis,  Lorena Anghel


Due to the notable change of channel width, power supply and clock frequency, IC technologies are rapidly approaching their ultimate limits of silicon. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result on unacceptable rates of soft errors and make further nanometer scaling more and more difficult. Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches). New error detection and correction techniques must come forth to maintain acceptable level of power dissipation, performance reduction and area increase. The error detection architecture described in this paper combines latch-based design and time redundancy techniques to achieve high error detection efficiency at low area and speed penalty. At the end of this paper, a finite state machine (FSM) circuit was used as test vehicle to validate the error detection architecture. The experiment results show that this error detection architecture has high error detection efficiency.