A Built-In Self-Calibration Scheme for Pipelined ADCs

Hsiu-Ming (Sherman) Chang1,  Kuan-Yu Lin2,  Chin-Hsuan Chen1,  Kwang-Ting (Tim) Cheng1
1ECE, UCSB, U.S.A., 2ITRI, Taiwan


There is a strong demand for both calibrating and testing the ADC performance before and after packaging for mixed-signal SoCs and SiPs. In this paper, we propose a built-in self-calibration scheme which offers digitally-controlled calibration of a pipelined ADC without using external stimulus. We further propose a self-testing strategy which uses the effective number of bits (ENOB) directly derived from the steady-state error of the self-calibration process for go/no-go testing as well as for performance binning. This test process will not incur any additional test time beyond the time required for calibration.