With growing complexity of System on Chip architectures and difficult time to market requirements, early design planning is very important. Design planning for physical design involves the deriving of information, useful to physical implementation of the chip, from the early design information available. Clock tree design and synthesis being a vital part of the design cycle, requires immense planning and experimentation. This paper proposes a way by which key clock tree information can be derived from as early as the register transfer level description of the design. The proposed methodology aids in analysing the clock tree structurally for being friendly to clock tree synthesis. It also enables the prototyping of the clock tree synthesis to understand the overhead it adds to the design. This information can be used to apply corrective feedback to the clock architecture and the physical implementation flow. The various aspects of the clock tree the flow generates along with their utility are presented in the paper with some testcase data.