Standby power reduction and SRAM cell optimization for 65nm technology

S Lakshminarayanan1,  Junho Joung1,  Geetha Narasimhan1,  Ravi Kapre1,  Miroslav Slanina1,  James Tung1,  Morgan Whately1,  C.L Hou2,  W.J Liao2,  S.C Lin2,  P-G Ma2,  C-W Fan2,  M-C Hsieh2,  F-C Liu2,  K-L Yeh2
1Cypress Semiconductor, 2United Microelectronics Corporation


Standby power is one of the most critical issues in low power chip applications. In this paper, we have investigated the effects of body bias and source bias through simulations on standby current (Isb) in 65nm technology. The simulation results show a 8X reduction in cell Isb at 125 C FF process corner with a 1.0V nmos body bias. Source biasing is shown to be a more effective technique for room temperature leakage reduction (~3X lower Isb@0.4V bias). We also describe a methodology to optimize the SRAM cell to meet all the process corners on the product. A 16Mb SRAM testchip was characterized for read disturb, write margin and read current margin at process corners by applying forward and reverse body biases to shift the cell transistor parameters. Different test sequences tailored for the parameter being measured were used to determine the failing bit count in each case. Voltage schmoo plots were generated from the measured data to obtain the Vccmin at each body bias condition. Based on the above, the threshold voltages of the cell transistors for maximum operating margin were derived.