Effect of Regularity-Enhanced Layout on Printability and Circuit Performance of Standard Cells

Hiroki SUNAGAWA1,  Haruhiko TERADA1,  Akira TSUCHIYA1,  Kazutoshi KOBAYASHI1,  Hidetoshi ONODERA2
1Department of Communications and Computer Engineering, Kyoto University., 2Department of Communications and Computer Engineering, Kyoto University. JST, CREST


As the minimum feature size shrinks down far below sub-wavelength, Restricted Design Rule(RDR) or layout regularity plays an important role for maintaining pattern fidelity in photo lithography. However, it also incurs overheads in layout area and circuit performances. Therefore it is important to find an appropriate level of regularity that gives the best trade-off among manufacturability, cost, and performance for each process technology. This paper discusses the effect of layout regularity on printability and circuit performance in 90--45nm processes by lithography simulation and real chip measurement. It is shown that we can focus more on circuit performance with less on layout regularity in a 90nm process while adequate amount of regularity is imperative for ensuring proper amount of lithographic process windows. We demonstrate the quantitative evaluation of the trade-off between printability and circuit performance.