PVT Variation Impact on Voltage Island Formation in MPSoC Design

Sohaib Majzoub1,  Resve Saleh1,  Rabab Ward2
1SoC Research Lab, Department of Electrical and Computer Engineering, University of British Columbia, 2Image Processing Lab, Department of Electrical & Computer Engineering, University of British Columbia


On-chip process, voltage, and temperature (PVT) variations are projected to be the major bottleneck in deep submicron design. Parameter variations can push performance and power budgets beyond their limits. In a voltage/frequency island (VFI) design, the initial VFI at pre-fabrication optimization may not fit a post-fabrication VFI. This can lead to a degradation in energy that completely offsets the advantage of using VFI. Finding a way for VFI formation in pre-fabrication optimization that is still valid in post-fabrication is a challenging task. Thus, it is crucial to include PVT variations in any power/performance VFI optimization algorithm to improve the design quality. In this paper, we present a methodology that can reduce the differences by including PVT variations in the optimization. We analyze the PVT impact for different PVT characteristics and propose ways to handle the issue with a penalty of only 3% .