New Word-line Driving Scheme for Suppressing Oxide-Tunneling Leakage in Sub-65-nm SRAMs

Ji-Hye Bong1,  Yong-Jin Kwon1,  Kyeong-Sik Min2,  Sung-Mo (Steve) Kang3
1Kookmin University, 2Kookmin University, UC Merced, 3UC Merced


A new word-line driving scheme is proposed in this paper for suppressing oxide-tunneling leakage in sub-65-nm devices. Reducing oxide-tunneling leakage is very essential in sub-65-nm era because of this tunneling leakage component becoming more and more serious comparing with the subthreshold component. In this paper, we propose raising word-line-off voltage higher than 0V thus relaxing the voltage stress across the oxides. This scheme can reduce not only oxide-tunneling leakage but also switching power because of the swing voltage of the word line being reduced. This scheme is verified using the 65-nm devices from the Predictive Technology Modeling group. The comparison shows the power consumption is lowered as much as 7.3%, 16.7%, and 35.3%, at 75C, 25C, and -25C, respectively, when all the rows are in sleep. And, during the read operation, the power consumption including both static and dynamic components is lowered as much as 28.0%, 24.6%, and 17.4%, at 75C, 25C, and -25C, respectively. At the write operation, amounts of power saving reaches 38.3%, 38.7%, and 40.3%, for 75C, 25C, and -25C, respectively, while showing very little delay overhead of word-line driving.