PETE: A Device/Circuit Analysis Framework for Evaluation and Comparison of Charge Based Emerging Devices

Charles Augustine1,  Arijit Raychowdhury2,  Kaushik Roy1
1Purdue University, 2Intel


This paper describes PETE*, a tool that has been developed for circuit/system level evaluation of nanoscaled devices. The motivation behind developing this tool is the fact that traditional device metrics like CV/Ion, Ioff or CV2f can no longer capture the true potential of semiconductor devices and underestimate or overestimate system level performance. At the same time, the development and deployment of compact models for any new device is a time-consuming effort, a task that can only be undertaken once the potential of the device has been established. Towards this end, we have developed PETE, so that device and circuit designers can perform a fast and reasonably accurate estimation of any new device without having to develop compact models. The inputs to PETE can be numerical I-V and C-V characteristics (derived from experiments or device simulations), and the tool can numerically evaluate a wide array of circuit/system level metrics pertaining to performance and power of logic gates, ring oscillators and mega-cells. We have evaluated emerging devices like sub-15nm Silicon transistors, Band-to-band-tunneling transistors, and Ferroelectric FETs with PETE and results obtained are within 5% accuracy when compared to a traditional SPICE based approach. PETE has been deployed on the nanoHUB ( for public use, and its simple web interface ensures that even a non-expert in circuits-system design can obtain accurate estimation of performance-power trade-off of any new technology.