Leakage Optimization Using Transistor-Level Dual Threshold Voltage Cell Library

Lin Yuan1,  Chandra Sekhar2,  Gang Qu3
1Synopsys Inc., 2Cisco Corp., 3Univ. of Maryland


Recently, a transistor level dual-Vth technique has been proposed, where transistors within the same cell are allowed to have different Vth to form the so-call mixed Vth (MVT) cell. However, it is impractical to build a full MVT cell library and include it in the standard dual Vth design flow. To make this practical, current approach is to add another design phase after technology mapping to replace high leakage cells with their low leakage MVT variants. We propose a method to seamlessly and effectively integrate transistor-level dual Vth technology into existing low power design flow. In this paper, we report our successful experience in applying this method to optimize leakage under timing constraints in an industrial design environment. For demonstration purpose, we build an MVT library based on only 15 cells in a standard library that contains 590 cells. On 11 ISCAS benchmarks and three industrial designs, this MVT library optimizes 27% of the design. Yet it gives an average of 9% and up to 25% leakage saving over the state-of-art gate level dual Vth design with a full size high Vth library.