Side Channel Aware Leakage Management in Nano-scale Cryptosystem-on-Chip (CoC)

Amirali Khatib Zadeh and Catherine Gebotys
University of Waterloo


This paper investigates the potential side channel threat to Cryptosystem-on-Chip (CoC) posed by the leakage power consumption. Side channel as an unintended source of compromising information is highly exploited in adversarial action against CoC. The increasing leakage power trend is shown to be highly correlated with increasing side channel threat. The effect of high threshold voltage (Vth) transistor assignment on improving side channel resistance is analyzed over CMOS technology scaling. This investigation shows growth of the leakage mechanisms, e.t. gate and band-to-band tunneling mechanisms, may reduce the effectiveness of the high Vth transistor assignment technique; however, high Vth devices can still be used in developing side channel resistant cryptosystem. The results obtained in this study can be used for the side channel aware leakage management in design and implementation of CoC in submicron technology. This research is crucial for side channel security of crypto core in sub-micron technology.