As CMOS technology feature sizes decrease, random within-die and inter-die process variations more and more jeopardizes SoC parametric and functional yield. Largely neglected in the State-Of-the-Art, dynamic energy consumption and power disipation becomes heavily affected. This paper describes a technique to systematically bring statistically correlated timing/energy variations all the way up from the device to the SoC level. We propose a flow for Variability Aware Modeling environment and apply it to a case study of industrial relevance.