Place and Route Considerations for Voltage Interpolated Designs

Kevin Brownell,  A. Durlov Khan,  David Brooks,  Gu-Yeon Wei
Harvard University


Voltage interpolation is a promising post fabrication technique for combating the effects of process variations. The benefits of voltage interpolation are well understood. Its implementation in a VLSI-CAD flow has been considered through the synthesis stage. In this paper we study the implications of place and route on voltage interpolation. We evaluate multiple placement strategies, and conclude that a hybridization of forced placement and cluster boxing techniques results in minimum overhead.