TuneLogic: Post-Silicon Tuning of Dual-Vdd Designs

Stephen Bijansky,  Adnan Aziz,  Scott Lee
University of Texas


Modern CMOS manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. It is our thesis that variability should be addressed post-manufacturing. The fundamental contribution we make is a dual-Vdd design style, and associated CAD algorithms, wherein we assign supply voltages to logic based on post-manufacturing analysis rather than designing with nominal values and guard banding. We perform a detailed case study of a custom designed pipelined multiplier using realistic process data. Our results show that for comparable yield and target delay, we can achieve significantly less power than a single-Vdd supply. For example, to achieve 100% yield at same target delay, TuneLogic uses 23.6 pJ/multiply while a single-Vdd design uses 34.6 pJ/multiply.