System-in-Package (SiP) design methodology integrates multiple dies which come from different vendors into a package. It is more advantageous than Printed Circuit Board (PCB) and System-on-a-Chip (SoC) design methodologies from the aspects of development cost, power consumption, time-to-market, and miniaturization. Since these integrated dies can be manufactured and tested separately, the best-quality SiP design can be achieved by using these best-quality dies. However, with considering cost constraint, the best-quality dies are not always qualified due to high cost. Thus, this paper proposes an algorithm to optimize the combination of dies with different yields and test coverages in an SiP such that a minimal cost is achieved subject to a quality constraint, or a least defect level is reached under the cost constraint. The proposed method significantly prunes the solution space, and efficiently determines the combination of dies.