Yield Evaluation of Analog Placement with Arbitrary Capacitor Ratio

Chen Jwu-E1,  Luo Pei-Wen2,  Wey Chin-Long1
1Department of Electrical Engineering, National Central University, Jhongli, Taoyuan, Taiwan, ROC., 2SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan, ROC.


Capacitance mismatch can be generally attributed two sources of errors: random mismatch and systematic mismatch. Random mismatch is caused by the process variation, while systematic mismatch is mainly due to asymmetrical layout and processing gradients. Common centroid structure may reduce the systematic mismatch, but not the random mismatch. Based on spatial correlation model, this study derives the relationship among correlation, mismatch, and variation of capacitance ratio. Results show that the placement of unit capacitance array with higher correlation results in lower mismatch and lower variation of capacitance ratio. For any arbitrary capacitance ratio, i.e., more than two capacitors, if the summation of correlation coefficients for all capacitance pairs is defined as “index”, the placement with higher index results in higher yield, where the yield is defined as the ratio of the acceptable designs over the sample size. In other words, one can find a near-optimal placement which has better yield by using the simple calculation of index, instead of the complicated circuit simulations.