A Half-Selection Free 10T SRAM Cell Using Column Lines Assist (CLA) Scheme

Shunsuke Okumura1,  Yusuke Iguchi1,  Shusuke Yoshimoto1,  Hidehiro Fujiwara1,  Hiroki Noguchi1,  Koji Nii2,  Hiroshi Kawaguchi1,  Masahiko Yoshimoto1
1Kobe University, 2Renesas Technology


We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is reduced by 25%, and the cell current is increased by 21%, compared with the prior 10T cell. The minimum operating voltage is lowered by the column line assist (CLA) scheme that suppresses write margin degradation. By measurement, we confirmed that the proposed 128-kb SRAM works at 0.56 V.