Uncriticality-directed Scheduling for Tackling Variation and Power Challenges

Toshinori Sato1 and Shingo Watanabe2
1Fukuoka University, 2Kyushu Institute of Technology


The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay has variability. Increasing the supply voltage to reduce the delay should not be a solution, since it increases power consumption, which is another serious problem in microprocessor designs. This paper proposes to combine recently-proposed configurable latency technique with an instruction scheduling technique considering instruction uncriticality. While relying only on the configurable latency technique degrades processor performance, the combination maintains it by executing only uncritical instructions in the long-latency units. The uncriticality-directed technique is extended for power reduction. This can be achieved by decreasing supply voltage for some variation-unaffected units. Detailed simulations show that the proposed scheduling technique improves processor performance by 7.0% on average over the conventional scheduling and that performance degradation from a variation-free processor is only 2.3% on average, when 2 of 4 integer ALUs are affected by variations. It also improves energy efficiency by 9.9% on average.