Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization

Kwangok Jeong1,  Andrew B. Kahng2,  Hailong Yao3
1ECE Department, University of California at San Diego, 2CSE and ECE Departments, University of California at San Diego, 3CSE Department, University of California at San Diego


This paper revisits and extends a general linear programming (LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgate biasing to minimize total leakage power under timing constraints. We minimize positive timing slack for each cell according to its leakage vs. delay sensitivity, so that unnecessary leakage power consumption is saved without degrading circuit performance. A key difference between our work and previous works is that we pre-process timing libraries to estimate the linear relation -- in every slew-load condition

-- between the gate delay and gate length by linear fitting and optimize total leakage power by estimating the optimal gate length for each gate using fast linear programming. With a 65GP industry testbed, and directly comparing with commercial tools, we show the QOR and runtime advantages of our method for the multi-Lgate and Lgate biasing knobs. We also show promising application to circuit timing legalization, a problem which frequently arises when implementation and signoff timers differ. Overall, our results show strong viability of LP based estimation and optimization: compared with the commercial tools, we: (1) shift the achievable delay-leakage tradeoff curve in a positive way, and (2) more accurately maintain prescribed timing constraints.