Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning

Xu He,  Sheqin Dong,  Yuchun Ma,  Xianlong Hong
tsinghua university


As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, is still necessary in 3D ICs to further optimize interconnects. Since those cross multi-layer nets in 3D ICs need to go through vertical interlayer via, the traditional buffer planning turns into simultaneous buffer and interlayer via planning in 3D ICs. In this paper, we give an efficient buffer and interlayer via planning algorithm with linear complexity, which make sure buffer and interlayer via are inserted as successfully as possible. Experimental results show the comparison of buffer planning between 2D ICs and 3D ICs. It is obviously that 3D ICs can significantly improve the interconnect delay.