A Comprehensive Model for Gate Delay under Process Variation and Different Driving and Loading Conditions

Mingzhi Gao,  Zuocang Ye,  Yan Wang,  Zhiping Yu
Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua Univ., Beijing


Gate delay models taking process variation into account are an essential part of ascendant statistical static timing analysis (SSTA). The statistical gate delay models in being, most of which take the forms of low order polynomials, are suffering from either enormous characterization cost or poor accuracy. We propose a statistical comprehensive gate delay model depicting both the effects of process variation and operating conditions including input slope and output load in this paper. With the help of effective dimension reduction, we can use only a couple of random variables to present the effect of process variation, which enables a simple modeling methodology as well as a cheap characterization process. This model can be changed into the polynomial forms required in some block based SSTA or directly used in Monte Carlo based SSTA. The error of the model is shown well below 5% compared with golden Monte Carlo data.