Level Matrix Propagation for Reliability Analysis of Nano-scale Circuits based on Probabilistic Transfer Matrix

Hicham Ezzat1 and Lirida Naviner2
1UFE (Universite Francaise d'Egypte), 2Telecom ParisTech


As CMOS technology is reaching the nanometer scale, transient and intermittent faults occurrence in logic circuits, which implies a reliability degradation, can no longer be neglected. This paper deals with reliability evaluation which is a critical parameter in circuit design. The proposed method is scalable, iterative and accelerates the reliability analysis.