Die-level Leakage Power Analysis of FinFET Circuits Considering Process Variations

Prateek Mishra,  Ajay Bhoj,  Niraj Jha
Princeton University


In the recent past, FinFETs have been touted as promising alternatives to planar CMOS owing to their superior short-channel characteristics. However, due to lithographic constraints, they are likely to suffer from the effects of process variations, which are manifested as large spreads in leakage current and delay in combinational logic circuits. In this work, we model the leakage probability density function (pdf) in shorted-gate (SG), independent-gate (IG)/low-power (LP), and mixed terminal (MT) FinFET standard logic cells, and examine the leakage tradeoffs in benchmark circuits synthesized using combinations of SG, LP and MT logic cells under the effect of process variations.

Using quasi-Monte Carlo mixed-mode device simulations in Sentaurus TCAD, we develop simple macromodels to capture the physical effects influencing the leakage spread in SG and IG-mode FinFET devices, and extend it to stacked devices in NAND/NOR gates. We also implement a methodology to obtain the overall leakage current distribution for large circuits (synthesized using SG/LP/MT-mode logic cells) using Latin hypercube sampling, considering spatial correlation on a quad-tree based grid. Results indicate that, starting from a 100% SG-mode circuit, the leakage spread/yield point can be improved considerably by suitably introducing LP-mode and MT-mode gates at iso-delay. We also show that increasing the fraction of LP/MT-mode gates (to reduce the mean and variance in leakage) in an SG-mode circuit, by permitting a delay slack, yields diminishing returns. Mixing LP- and MT-mode gates with SG-mode gates appears to be a promising synthesis strategy that can leverage the leakage tradeoffs offered by FinFET standard cells.