Modeling and Analysis of III-V Logic FETs for Devices and Circuits: Sub-22nm Technology III-V SRAM Cell Design

Saeroonter Oh,  Jeongha Park,  S. Simon Wong,  H.-S. Philip Wong
Stanford University


A compact model of III-V HFETs is developed for digital logic circuit applications such as a 6T-SRAM cell. We study sub-22nm technology III-V SRAM circuit design via III-V MOSFETs with a thin high-k dielectric for low gate tunneling current, and optimized extrinsic structure for minimum parasitic capacitance. We investigate the drawbacks of a weak PMOS device in a SRAM cell and propose a minimum requirement for III-V PMOS for SRAM to be viable.